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<ul>
<li><a href="#about" style=" font-size: 16px;">Synthesis Messages</a></li>
<li><a href="#summary" style=" font-size: 16px;">Synthesis Details</a></li>
<li><a href="#resource" style=" font-size: 16px;">Resource</a>
<ul>
<li><a href="#usage" style=" font-size: 14px;">Resource Usage Summary</a></li>
<li><a href="#utilization" style=" font-size: 14px;">Resource Utilization Summary</a></li>
</ul>
</li>
<li><a href="#timing" style=" font-size: 16px;">Timing</a>
<ul>
<li><a href="#clock" style=" font-size: 14px;">Clock Summary</a></li>
<li><a href="#performance" style=" font-size: 14px;">Max Frequency Summary</a></li>
<li><a href="#detail timing" style=" font-size: 14px;">Detail Timing Paths Informations</a></li>
</ul>
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<div id="content">
<h1><a name="about">Synthesis Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>GowinSynthesis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>D:\FPGA\TangNano-9K-example\hdmi\src\dualshock.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\gowin_clkdiv\gowin_clkdiv.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\gowin_rpll\gowin_rpll.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_defines.vh<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_enc.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_openldi.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_tcard.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_term.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_tmds.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_utils.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\hdmi\svo_vdma.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\reset_sync.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\svo_hdmi.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\top.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\tx.v<br>
D:\FPGA\TangNano-9K-example\hdmi\src\uart.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_crc32.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_match.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_mem_ctrl.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_AO_0\gw_ao_top.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\GAO\GW_CON\gw_con_top.v<br>
D:\Gowin\Gowin_V1.9.9_x64\IDE\data\ipcores\gw_jtag.v<br>
D:\FPGA\TangNano-9K-example\hdmi\impl\gwsynthesis\RTL_GAO\gw_gao_top.v<br>
</td>
</tr>
<tr>
<td class="label">GowinSynthesis Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.9 (64-bit)</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NR-LV9QN88PC6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NR-9</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Fri Apr 19 15:27:05 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2023 Gowin Semiconductor Corporation. ALL rights reserved.</td>
</tr>
</table>
<h1><a name="summary">Synthesis Details</a></h1>
<table class="summary_table">
<tr>
<td class="label">Top Level Module</td>
<td>top</td>
</tr>
<tr>
<td class="label">Synthesis Process</td>
<td>Running parser:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0.781s, Elapsed time = 0h 0m 1s, Peak memory usage = 267.082MB<br/>Running netlist conversion:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0s, Peak memory usage = 0MB<br/>Running device independent optimization:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 0: CPU time = 0h 0m 0.078s, Elapsed time = 0h 0m 0.199s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.055s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Optimizing Phase 2: CPU time = 0h 0m 0.218s, Elapsed time = 0h 0m 0.248s, Peak memory usage = 267.082MB<br/>Running inference:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 0: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.044s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 1: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.016s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.037s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Inferring Phase 3: CPU time = 0h 0m 0.031s, Elapsed time = 0h 0m 0.018s, Peak memory usage = 267.082MB<br/>Running technical mapping:<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 0: CPU time = 0h 0m 0.281s, Elapsed time = 0h 0m 0.316s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 1: CPU time = 0h 0m 0.046s, Elapsed time = 0h 0m 0.028s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 2: CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.019s, Peak memory usage = 267.082MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 3: CPU time = 0h 0m 5s, Elapsed time = 0h 0m 6s, Peak memory usage = 272.980MB<br/>&nbsp;&nbsp;&nbsp;&nbsp;Tech-Mapping Phase 4: CPU time = 0h 0m 0.125s, Elapsed time = 0h 0m 0.203s, Peak memory usage = 272.980MB<br/>Generate output files:<br/>&nbsp;&nbsp;&nbsp;&nbsp;CPU time = 0h 0m 0s, Elapsed time = 0h 0m 0.143s, Peak memory usage = 272.980MB<br/></td>
</tr>
<tr>
<td class="label">Total Time and Memory Usage</td>
<td>CPU time = 0h 0m 6s, Elapsed time = 0h 0m 8s, Peak memory usage = 272.980MB</td>
</tr>
</table>
<h1><a name="resource">Resource</a></h1>
<h2><a name="usage">Resource Usage Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
</tr>
<tr>
<td class="label"><b>I/O Port </b></td>
<td>19</td>
</tr>
<tr>
<td class="label"><b>I/O Buf </b></td>
<td>15</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspIBUF</td>
<td>6</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOBUF</td>
<td>5</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspELVDS_OBUF</td>
<td>4</td>
</tr>
<tr>
<td class="label"><b>Register </b></td>
<td>983</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFF</td>
<td>51</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFE</td>
<td>337</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFS</td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFSE</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFR</td>
<td>105</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFRE</td>
<td>164</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFP</td>
<td>8</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFPE</td>
<td>34</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFC</td>
<td>52</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFCE</td>
<td>205</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspDFFNE</td>
<td>16</td>
</tr>
<tr>
<td class="label"><b>LUT </b></td>
<td>1383</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT2</td>
<td>191</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT3</td>
<td>484</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspLUT4</td>
<td>708</td>
</tr>
<tr>
<td class="label"><b>MUX </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspMUX16</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>ALU </b></td>
<td>141</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspALU</td>
<td>141</td>
</tr>
<tr>
<td class="label"><b>SSRAM </b></td>
<td>16</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16S4</td>
<td>9</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspRAM16SDP4</td>
<td>7</td>
</tr>
<tr>
<td class="label"><b>INV </b></td>
<td>19</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspINV</td>
<td>19</td>
</tr>
<tr>
<td class="label"><b>IOLOGIC </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspOSER10</td>
<td>3</td>
</tr>
<tr>
<td class="label"><b>BSRAM </b></td>
<td>3</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspSDPB</td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsppROM</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>CLOCK </b></td>
<td>2</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspCLKDIV</td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbsprPLL</td>
<td>1</td>
</tr>
<tr>
<td class="label"><b>Black Box </b></td>
<td>1</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp&nbsp&nbspGW_JTAG</td>
<td>1</td>
</tr>
</table>
<h2><a name="utilization">Resource Utilization Summary</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Resource</b></td>
<td><b>Usage</b></td>
<td><b>Utilization</b></td>
</tr>
<tr>
<td class="label">Logic</td>
<td>1647(1410 LUT, 141 ALU, 16 RAM16) / 8640</td>
<td>20%</td>
</tr>
<tr>
<td class="label">Register</td>
<td>983 / 6693</td>
<td>15%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as Latch</td>
<td>0 / 6693</td>
<td>0%</td>
</tr>
<tr>
<td class="label">&nbsp&nbsp--Register as FF</td>
<td>983 / 6693</td>
<td>15%</td>
</tr>
<tr>
<td class="label">BSRAM</td>
<td>3 / 26</td>
<td>12%</td>
</tr>
</table>
<h1><a name="timing">Timing</a></h1>
<h2><a name="clock">Clock Summary:</a></h2>
<table class="summary_table">
<tr>
<th>Clock Name</th>
<th>Type</th>
<th>Period</th>
<th>Frequency(MHz)</th>
<th>Rise</th>
<th>Fall</th>
<th>Source</th>
<th>Master</th>
<th>Object</th>
</tr>
<tr>
<td>clk</td>
<td>Base</td>
<td>37.037</td>
<td>27.0</td>
<td>0.000</td>
<td>18.519</td>
<td> </td>
<td> </td>
<td>clk_ibuf/I </td>
</tr>
<tr>
<td>controller/pls/W_scan_seq_pls</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>controller/pls/O_SCAN_SEQ_PLS_s0/Q </td>
</tr>
<tr>
<td>sclk_5</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>sclk_s2/Q </td>
</tr>
<tr>
<td>controller/pls/W_TXSET</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>controller/pls/W_TXSET_s/F </td>
</tr>
<tr>
<td>controller/txd/n4_13</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>controller/txd/n4_s6/O </td>
</tr>
<tr>
<td>controller/pls/joystick_clk_d_4</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>controller/pls/joystick_clk_d_s0/F </td>
</tr>
<tr>
<td>controller/n50_21</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>controller/n50_s1/F </td>
</tr>
<tr>
<td>gw_gao_inst_0/u_icon_top/n19_6</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>gw_gao_inst_0/u_icon_top/n19_s2/O </td>
</tr>
<tr>
<td>gw_gao_inst_0/u_la0_top/n15_6</td>
<td>Base</td>
<td>20.000</td>
<td>50.0</td>
<td>0.000</td>
<td>10.000</td>
<td> </td>
<td> </td>
<td>gw_gao_inst_0/u_la0_top/n15_s2/O </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.0</td>
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>7.937</td>
<td>126.0</td>
<td>0.000</td>
<td>3.968</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>15.873</td>
<td>63.0</td>
<td>0.000</td>
<td>7.937</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>u_pll/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>23.810</td>
<td>42.0</td>
<td>0.000</td>
<td>11.905</td>
<td>clk_ibuf/I</td>
<td>clk</td>
<td>u_pll/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>39.683</td>
<td>25.2</td>
<td>0.000</td>
<td>19.841</td>
<td>u_pll/rpll_inst/CLKOUT</td>
<td>u_pll/rpll_inst/CLKOUT.default_gen_clk</td>
<td>u_div_5/clkdiv_inst/CLKOUT </td>
</tr>
</table>
<h2><a name="performance">Max Frequency Summary:</a></h2>
<table class="summary_table">
<tr>
<th>No.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>clk</td>
<td>27.0(MHz)</td>
<td>94.9(MHz)</td>
<td>7</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>sclk_5</td>
<td>50.0(MHz)</td>
<td>172.5(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>controller/pls/W_TXSET</td>
<td>50.0(MHz)</td>
<td>128.0(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>controller/txd/n4_13</td>
<td>50.0(MHz)</td>
<td>342.8(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>controller/pls/joystick_clk_d_4</td>
<td>50.0(MHz)</td>
<td>747.2(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>controller/n50_21</td>
<td>50.0(MHz)</td>
<td>409.4(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>7</td>
<td>gw_gao_inst_0/u_icon_top/n19_6</td>
<td>50.0(MHz)</td>
<td>747.2(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>8</td>
<td>gw_gao_inst_0/u_la0_top/n15_6</td>
<td>50.0(MHz)</td>
<td>747.2(MHz)</td>
<td>1</td>
<td>TOP</td>
</tr>
<tr>
<td>9</td>
<td>u_div_5/clkdiv_inst/CLKOUT.default_gen_clk</td>
<td>25.2(MHz)</td>
<td>42.0(MHz)</td>
<td>17</td>
<td>TOP</td>
</tr>
</table>
<h2><a name="detail timing">Detail Timing Paths Information</a></h2>
<h3>Path&nbsp1</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-12.696</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>383.981</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.285</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_ypos_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>370.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>controller/O_RXD_2_1_s1/CLK</td>
</tr>
<tr>
<td>370.938</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>controller/O_RXD_2_1_s1/Q</td>
</tr>
<tr>
<td>371.418</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n412_s2/I1</td>
</tr>
<tr>
<td>372.517</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n412_s2/F</td>
</tr>
<tr>
<td>372.997</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s11/I2</td>
</tr>
<tr>
<td>373.819</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n430_s11/F</td>
</tr>
<tr>
<td>374.299</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>375.398</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n436_s7/F</td>
</tr>
<tr>
<td>375.878</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>376.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>direct_1_s5/F</td>
</tr>
<tr>
<td>376.984</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>377.806</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n463_s17/F</td>
</tr>
<tr>
<td>378.286</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>379.318</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>n463_s12/F</td>
</tr>
<tr>
<td>379.798</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>380.620</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n431_s7/F</td>
</tr>
<tr>
<td>381.100</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n453_s13/I2</td>
</tr>
<tr>
<td>381.922</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n453_s13/F</td>
</tr>
<tr>
<td>382.402</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n462_s8/I1</td>
</tr>
<tr>
<td>383.501</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n462_s8/F</td>
</tr>
<tr>
<td>383.981</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>axis_ypos_0_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>371.352</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>132</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>371.715</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>axis_ypos_0_s2/CLK</td>
</tr>
<tr>
<td>371.685</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>axis_ypos_0_s2</td>
</tr>
<tr>
<td>371.285</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>axis_ypos_0_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 8.243, 61.053%; route: 4.800, 35.552%; tC2Q: 0.458, 3.395%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp2</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-12.419</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>383.704</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.285</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>370.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>controller/O_RXD_2_1_s1/CLK</td>
</tr>
<tr>
<td>370.938</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>controller/O_RXD_2_1_s1/Q</td>
</tr>
<tr>
<td>371.418</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n412_s2/I1</td>
</tr>
<tr>
<td>372.517</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n412_s2/F</td>
</tr>
<tr>
<td>372.997</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s11/I2</td>
</tr>
<tr>
<td>373.819</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n430_s11/F</td>
</tr>
<tr>
<td>374.299</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>375.398</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n436_s7/F</td>
</tr>
<tr>
<td>375.878</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>376.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>direct_1_s5/F</td>
</tr>
<tr>
<td>376.984</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>377.806</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n463_s17/F</td>
</tr>
<tr>
<td>378.286</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>379.318</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>n463_s12/F</td>
</tr>
<tr>
<td>379.798</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>380.620</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n431_s7/F</td>
</tr>
<tr>
<td>381.100</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n453_s13/I2</td>
</tr>
<tr>
<td>381.922</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n453_s13/F</td>
</tr>
<tr>
<td>382.402</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n453_s12/I2</td>
</tr>
<tr>
<td>383.224</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n453_s12/F</td>
</tr>
<tr>
<td>383.704</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>axis_xpos_0_s2/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>371.352</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>132</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>371.715</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>axis_xpos_0_s2/CLK</td>
</tr>
<tr>
<td>371.685</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>axis_xpos_0_s2</td>
</tr>
<tr>
<td>371.285</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>axis_xpos_0_s2</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>10</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.966, 60.237%; route: 4.800, 36.297%; tC2Q: 0.458, 3.466%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp3</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-11.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>382.402</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.285</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>370.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>controller/O_RXD_2_1_s1/CLK</td>
</tr>
<tr>
<td>370.938</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>controller/O_RXD_2_1_s1/Q</td>
</tr>
<tr>
<td>371.418</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n412_s2/I1</td>
</tr>
<tr>
<td>372.517</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n412_s2/F</td>
</tr>
<tr>
<td>372.997</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s11/I2</td>
</tr>
<tr>
<td>373.819</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n430_s11/F</td>
</tr>
<tr>
<td>374.299</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>375.398</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n436_s7/F</td>
</tr>
<tr>
<td>375.878</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>376.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>direct_1_s5/F</td>
</tr>
<tr>
<td>376.984</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>377.806</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n463_s17/F</td>
</tr>
<tr>
<td>378.286</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s12/I0</td>
</tr>
<tr>
<td>379.318</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>n463_s12/F</td>
</tr>
<tr>
<td>379.798</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n431_s7/I2</td>
</tr>
<tr>
<td>380.620</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n431_s7/F</td>
</tr>
<tr>
<td>381.100</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n431_s9/I2</td>
</tr>
<tr>
<td>381.922</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n431_s9/F</td>
</tr>
<tr>
<td>382.402</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spiout1_1_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>371.352</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>132</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>371.715</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spiout1_1_s0/CLK</td>
</tr>
<tr>
<td>371.685</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spiout1_1_s0</td>
</tr>
<tr>
<td>371.285</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spiout1_1_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.144, 59.921%; route: 4.320, 36.235%; tC2Q: 0.458, 3.844%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp4</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-11.117</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>382.402</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.285</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_2_1_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>370.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>controller/O_RXD_2_1_s1/CLK</td>
</tr>
<tr>
<td>370.938</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>5</td>
<td>controller/O_RXD_2_1_s1/Q</td>
</tr>
<tr>
<td>371.418</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n412_s2/I1</td>
</tr>
<tr>
<td>372.517</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n412_s2/F</td>
</tr>
<tr>
<td>372.997</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s11/I2</td>
</tr>
<tr>
<td>373.819</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n430_s11/F</td>
</tr>
<tr>
<td>374.299</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n436_s7/I1</td>
</tr>
<tr>
<td>375.398</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n436_s7/F</td>
</tr>
<tr>
<td>375.878</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>direct_1_s5/I3</td>
</tr>
<tr>
<td>376.504</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>5</td>
<td>direct_1_s5/F</td>
</tr>
<tr>
<td>376.984</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s17/I2</td>
</tr>
<tr>
<td>377.806</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n463_s17/F</td>
</tr>
<tr>
<td>378.286</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n437_s7/I2</td>
</tr>
<tr>
<td>379.108</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n437_s7/F</td>
</tr>
<tr>
<td>379.588</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n429_s8/I0</td>
</tr>
<tr>
<td>380.620</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n429_s8/F</td>
</tr>
<tr>
<td>381.100</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n429_s9/I2</td>
</tr>
<tr>
<td>381.922</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n429_s9/F</td>
</tr>
<tr>
<td>382.402</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spiout1_3_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>371.352</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>132</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>371.715</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spiout1_3_s0/CLK</td>
</tr>
<tr>
<td>371.685</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spiout1_3_s0</td>
</tr>
<tr>
<td>371.285</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spiout1_3_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>9</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 7.144, 59.921%; route: 4.320, 36.235%; tC2Q: 0.458, 3.844%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
</table>
<br/>
<h3>Path&nbsp5</h3>
<b>Path Summary:</b></br>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-10.235</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>381.520</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>371.285</td>
</tr>
<tr>
<td class="label">From</td>
<td>controller/O_RXD_1_2_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>spiout1_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>controller/n50_21[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>clk[F]</td>
</tr>
</table>
<b>Data Arrival Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>controller/n50_21</td>
</tr>
<tr>
<td>370.000</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>24</td>
<td>controller/n50_s1/F</td>
</tr>
<tr>
<td>370.480</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>controller/O_RXD_1_2_s1/CLK</td>
</tr>
<tr>
<td>370.938</td>
<td>0.458</td>
<td>tC2Q</td>
<td>FF</td>
<td>4</td>
<td>controller/O_RXD_1_2_s1/Q</td>
</tr>
<tr>
<td>371.418</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s9/I1</td>
</tr>
<tr>
<td>372.517</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n430_s9/F</td>
</tr>
<tr>
<td>372.997</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n430_s7/I0</td>
</tr>
<tr>
<td>374.029</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n430_s7/F</td>
</tr>
<tr>
<td>374.509</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n432_s7/I0</td>
</tr>
<tr>
<td>375.541</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>n432_s7/F</td>
</tr>
<tr>
<td>376.021</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n463_s14/I3</td>
</tr>
<tr>
<td>376.647</td>
<td>0.626</td>
<td>tINS</td>
<td>FF</td>
<td>4</td>
<td>n463_s14/F</td>
</tr>
<tr>
<td>377.127</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n465_s9/I0</td>
</tr>
<tr>
<td>378.159</td>
<td>1.032</td>
<td>tINS</td>
<td>FF</td>
<td>2</td>
<td>n465_s9/F</td>
</tr>
<tr>
<td>378.639</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>psstatus_2_s4/I1</td>
</tr>
<tr>
<td>379.738</td>
<td>1.099</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>psstatus_2_s4/F</td>
</tr>
<tr>
<td>380.218</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>n432_s8/I2</td>
</tr>
<tr>
<td>381.040</td>
<td>0.822</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>n432_s8/F</td>
</tr>
<tr>
<td>381.520</td>
<td>0.480</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>spiout1_0_s0/D</td>
</tr>
</table>
<b>Data Required Path:</b>
<table class="summary_table">
<tr>
<th>AT</th>
<th>DELAY</th>
<th>TYPE</th>
<th>RF</th>
<th>FANOUT</th>
<th>NODE</th>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td> </td>
<td> </td>
<td> </td>
<td>clk</td>
</tr>
<tr>
<td>370.370</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>clk_ibuf/I</td>
</tr>
<tr>
<td>371.352</td>
<td>0.982</td>
<td>tINS</td>
<td>RR</td>
<td>132</td>
<td>clk_ibuf/O</td>
</tr>
<tr>
<td>371.715</td>
<td>0.363</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>spiout1_0_s0/CLK</td>
</tr>
<tr>
<td>371.685</td>
<td>-0.030</td>
<td>tUnc</td>
<td> </td>
<td> </td>
<td>spiout1_0_s0</td>
</tr>
<tr>
<td>371.285</td>
<td>-0.400</td>
<td>tSu</td>
<td> </td>
<td>1</td>
<td>spiout1_0_s0</td>
</tr>
</table>
<b>Path Statistics:</b>
<table class="summary_table">
<tr>
<td class="label">Clock Skew:</td>
<td>0.865</td>
</tr>
<tr>
<td class="label">Setup Relationship:</td>
<td>0.370</td>
</tr>
<tr>
<td class="label">Logic Level:</td>
<td>8</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
<tr>
<td class="label">Arrival Data Path Delay:</td><td> cell: 6.742, 61.067%; route: 3.840, 34.782%; tC2Q: 0.458, 4.151%</td></tr>
<tr>
<td class="label">Required Clock Path Delay:</td><td> cell: 0.000, 0.000%; route: 0.480, 100.000%</td></tr>
</table>
<br/>
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